Intel 253666-024US - Manual (Page 197)

Vol. 2A 3-151
INSTRUCTION SET REFERENCE, A-M
CMPXCHG—Compare and Exchange
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R
prefix permits access to additional registers (R8-R15). Use of the REX.W prefix
promotes operation to 64 bits. See the summary chart at the beginning of this
section for encoding data and limits.
IA-32 Architecture Compatibility
This instruction is not supported on Intel processors earlier than the Intel486 proces-
sors.
Operation
(* Accumulator = AL, AX, EAX, or RAX depending on whether a byte, word, doubleword, or
quadword comparison is being performed *)
IF accumulator = DEST
THEN
ZF ← 1;
DEST ← SRC;
ELSE
ZF ← 0;
accumulator ← DEST;
FI;
Flags Affected
The ZF flag is set if the values in the destination operand and register AL, AX, or EAX
are equal; otherwise it is cleared. The CF, PF, AF, SF, and OF flags are set according to
the results of the comparison operation.
Protected Mode Exceptions
#GP(0) If the destination is located in a non-writable segment.
If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment
selector.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
#UD If the LOCK prefix is used but the destination is not a memory
operand.