Intel 253666-024US - Manual (Page 499)

Vol. 2A 3-453
INSTRUCTION SET REFERENCE, A-M
IDIV—Signed Divide
IDIV—Signed Divide
Description
Divides the (signed) value in the AX, DX:AX, or EDX:EAX (dividend) by the source
operand (divisor) and stores the result in the AX (AH:AL), DX:AX, or EDX:EAX regis-
ters. The source operand can be a general-purpose register or a memory location.
The action of this instruction depends on the operand size (dividend/divisor).
Non-integral results are truncated (chopped) towards 0. The remainder is always less
than the divisor in magnitude. Overflow is indicated with the #DE (divide error)
exception rather than with the CF flag.
In 64-bit mode, the instruction’s default operation size is 32 bits. Use of the REX.R
prefix permits access to additional registers (R8-R15). Use of the REX.W prefix
promotes operation to 64 bits. In 64-bit mode when REX.W is applied, the instruction
divides the signed value in RDX:RAX by the source operand. RAX contains a 64-bit
quotient; RDX contains a 64-bit remainder.
See the summary chart at the beginning of this section for encoding data and limits.
See Table 3-55.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
F6 /7 IDIV r/m8 Valid Valid Signed divide AX by r/m8, with result
stored in: AL ← Quotient, AH ←
Remainder.
REX + F6 /7 IDIV r/m8* Valid N.E. Signed divide AX by r/m8, with result
stored in AL ← Quotient, AH ←
Remainder.
F7 /7 IDIV r/m16 Valid Valid Signed divide DX:AX by r/m16, with
result stored in AX ← Quotient, DX ←
Remainder.
F7 /7 IDIV r/m32 Valid Valid Signed divide EDX:EAX by r/m32, with
result stored in EAX ← Quotient, EDX ←
Remainder.
REX.W + F7 /7 IDIV r/m64 Valid N.E. Signed divide RDX:RAX by r/m64, with
result stored in RAX ← Quotient, RDX ←
Remainder.
NOTES:
* In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix is
used: AH, BH, CH, DH.