Intel 253666-024US - Manual (Page 343)

Vol. 2A 3-297
INSTRUCTION SET REFERENCE, A-M
FBSTP—Store BCD Integer and Pop
nation operand. If the invalid-operation exception is masked, the packed BCD indef-
inite value is stored in memory.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
DEST ← BCD(ST(0));
PopRegisterStack;
FPU Flags Affected
C1 Set to 0 if stack underflow occurred.
Set if result was rounded up; cleared otherwise.
C0, C2, C3 Undefined.
Floating-Point Exceptions
#IS Stack underflow occurred.
#IA Converted value that exceeds 18 BCD digits in length.
Source operand is an SNaN, QNaN, ±∞, or in an unsupported
format.
#P Value cannot be represented exactly in destination format.
Protected Mode Exceptions
#GP(0) If a segment register is being loaded with a segment selector
that points to a non-writable segment.
If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
If the DS, ES, FS, or GS register contains a NULL segment
selector.
#SS(0) If a memory operand effective address is outside the SS
segment limit.
#NM CR0.EM[bit 2] or CR0.TS[bit 3] = 1.
#PF(fault-code) If a page fault occurs.
#AC(0) If alignment checking is enabled and an unaligned memory
reference is made while the current privilege level is 3.
#UD If the LOCK prefix is used.
Real-Address Mode Exceptions
#GP If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
#SS If a memory operand effective address is outside the SS
segment limit.