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Intel 253666-024US User Manual

Page 194

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3-148 Vol. 2A

CMPSS—Compare Scalar Single-Precision Floating-Point Values

INSTRUCTION SET REFERENCE, A-M

CMPSS for less-than

__m128 _mm_cmplt_ss(__m128 a, __m128 b)

CMPSS for less-than-or-equal

__m128 _mm_cmple_ss(__m128 a, __m128 b)

CMPSS for greater-than

__m128 _mm_cmpgt_ss(__m128 a, __m128 b)

CMPSS for greater-than-or-equal__m128 _mm_cmpge_ss(__m128 a, __m128 b)
CMPSS for inequality

__m128 _mm_cmpneq_ss(__m128 a, __m128 b)

CMPSS for not-less-than

__m128 _mm_cmpnlt_ss(__m128 a, __m128 b)

CMPSS for not-greater-than

__m128 _mm_cmpngt_ss(__m128 a, __m128 b)

CMPSS for not-greater-than-or-equal__m128 _mm_cmpnge_ss(__m128 a, __m128 b)
CMPSS for ordered

__m128 _mm_cmpord_ss(__m128 a, __m128 b)

CMPSS for unordered

__m128 _mm_cmpunord_ss(__m128 a, __m128 b)

CMPSS for not-less-than-or-equal__m128 _mm_cmpnle_ss(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

Invalid if SNaN operand, Invalid if QNaN and predicate as listed in above table,
Denormal.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#NM

If CR0.TS[bit 3] = 1.

#XM

If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.

#UD

If an unmasked SIMD floating-point exception and CR4.OSXM-

MEXCPT[bit 10] = 0.

If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
If CPUID.01H:EDX.SSE[bit 25] = 0.

#UD

If the LOCK prefix is used.

#AC(0)

If alignment checking is enabled and an unaligned memory

reference is made while the current privilege level is 3.

Real-Address Mode Exceptions

#GP(0)

If any part of the operand lies outside the effective address

space from 0 to FFFFH.

#NM

If CR0.TS[bit 3] = 1.

#XM

If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.