Intel 253666-024US User Manual

Page 747

Vol. 2A 3-701

INSTRUCTION SET REFERENCE, A-M

MULPS—Multiply Packed Single-Precision Floating-Point Values

Description

Performs a SIMD multiply of the four packed single-precision floating-point values
from the source operand (second operand) and the destination operand (first
operand), and stores the packed single-precision floating-point results in the desti-
nation operand. The source operand can be an XMM register or a 128-bit memory
location. The destination operand is an XMM register. See Figure 10-5 in the Intel®
64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an illustra-
tion of a SIMD single-precision floating-point operation.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation

DEST[31:0] ← DEST[31:0]

∗

SRC[31:0];

DEST[63:32] ← DEST[63:32]

∗

SRC[63:32];

DEST[95:64] ← DEST[95:64]

∗

SRC[95:64];

DEST[127:96] ← DEST[127:96]

∗

SRC[127:96];

Intel C/C++ Compiler Intrinsic Equivalent

MULPS

__m128 _mm_mul_ps(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Precision, Denormal.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments.

If a memory operand is not aligned on a 16-byte boundary,

regardless of segment.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

#NM

If CR0.TS[bit 3] = 1.

Opcode

Instruction

64-Bit

Mode

Compat/

Leg Mode

Description

0F 59 /r

MULPS xmm1,

xmm2/m128

Valid

Multiply packed single-precision

floating-point values in xmm2/mem by

xmm1.