Intel 253666-024US - Manual (Page 566)

3-520 Vol. 2A LAR—Load Access Rights Byte
INSTRUCTION SET REFERENCE, A-M
LAR—Load Access Rights Byte
Description
Loads the access rights from the segment descriptor specified by the second operand
(source operand) into the first operand (destination operand) and sets the ZF flag in
the flag register. The source operand (which can be a register or a memory location)
contains the segment selector for the segment descriptor being accessed. If the
source operand is a memory address, only 16 bits of data are accessed. The destina-
tion operand is a general-purpose register.
The processor performs access checks as part of the loading process. Once loaded in
the destination register, software can perform additional checks on the access rights
information.
When the operand size is 32 bits, the access rights for a segment descriptor include
the type and DPL fields and the S, P, AVL, D/B, and G flags, all of which are located in
the second doubleword (bytes 4 through 7) of the segment descriptor. The double-
word is masked by 00FXFF00H before it is loaded into the destination operand. When
the operand size is 16 bits, the access rights include the type and DPL fields. Here,
the two lower-order bytes of the doubleword are masked by FF00H before being
loaded into the destination operand.
This instruction performs the following checks before it loads the access rights in the
destination register:
• Checks that the segment selector is not NULL.
• Checks that the segment selector points to a descriptor that is within the limits of
the GDT or LDT being accessed
• Checks that the descriptor type is valid for this instruction. All code and data
segment descriptors are valid for (can be accessed with) the LAR instruction. The
valid system segment and gate descriptor types are given in Table 3-57.
Opcode Instruction 64-Bit Mode Compat/
Leg Mode
Description
0F 02 /r LAR r16, r16/m16 Valid Valid r16 ← r16/m16 masked by
FF00H.
0F 02 /r LAR r32, r32/m16 1 Valid Valid r32 ← r32/m16 masked by
00FxFF00H
REX.W +
0F 02 /r
LAR r64, r32/m16 1 Valid N.E. r64 ← r32/m16 masked by
00FxFF00H and zero extended
NOTES:
1. For all loads (regardless of source or destination sizing) only bits 16-0 are used. Other bits are
ignored.