Intel 253666-024US - Manual (Page 573)

Vol. 2A 3-527
INSTRUCTION SET REFERENCE, A-M
LDMXCSR—Load MXCSR Register
LDMXCSR—Load MXCSR Register
Description
Loads the source operand into the MXCSR control/status register. The source
operand is a 32-bit memory location. See “MXCSR Control and Status Register” in
Chapter 10, of the Intel® 64 and IA-32 Architectures Software Developer’s Manual,
Volume 1, for a description of the MXCSR register and its contents.
The LDMXCSR instruction is typically used in conjunction with the STMXCSR instruc-
tion, which stores the contents of the MXCSR register in memory.
The default MXCSR value at reset is 1F80H.
If a LDMXCSR instruction clears a SIMD floating-point exception mask bit and sets
the corresponding exception flag bit, a SIMD floating-point exception will not be
immediately generated. The exception will be generated only upon the execution of
the next SSE or SSE2 instruction that causes that particular SIMD floating-point
exception to be reported.
This instruction’s operation is the same in non-64-bit modes and 64-bit mode.
Operation
MXCSR ← m32;
C/C++ Compiler Intrinsic Equivalent
_mm_setcsr(unsigned int i)
Numeric Exceptions
None.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS, or GS segments.
For an attempt to set reserved bits in MXCSR.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
0F,AE,/2 LDMXCSR m32 Valid Valid Load MXCSR register from m32.