Intel 253666-024US - Manual (Page 236)

3-190 Vol. 2A CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-Precision Floating-
Point Values
INSTRUCTION SET REFERENCE, A-M
CVTDQ2PD—Convert Packed Doubleword Integers to Packed Double-
Precision Floating-Point Values
Description
Converts two packed signed doubleword integers in the source operand (second
operand) to two packed double-precision floating-point values in the destination
operand (first operand).
The source operand can be an XMM register or a 64-bit memory location. The desti-
nation operand is an XMM register. When the source operand is an XMM register, the
packed integers are located in the low quadword of the register.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[63:0] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[31:0]);
DEST[127:64] ← Convert_Integer_To_Double_Precision_Floating_Point(SRC[63:32]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTDQ2PD __m128d _mm_cvtepi32_pd(__m128i a)
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CR0.TS[bit 3] = 1.
#UD If CR0.EM[bit 2] = 1.
If CR4.OSFXSR[bit 9] = 0.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F E6 CVTDQ2PD xmm1,
xmm2/m64
Valid Valid Convert two packed signed
doubleword integers from
xmm2/m128 to two packed
double-precision floating-point
values in xmm1.