Intel 253666-024US - Manual (Page 238)

3-192 Vol. 2A CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-Precision Floating-
Point Values
INSTRUCTION SET REFERENCE, A-M
CVTDQ2PS—Convert Packed Doubleword Integers to Packed Single-
Precision Floating-Point Values
Description
Converts four packed signed doubleword integers in the source operand (second
operand) to four packed single-precision floating-point values in the destination
operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register. When a conversion is inexact, rounding is
performed according to the rounding control bits in the MXCSR register.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[31:0]);
DEST[63:32] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[63:32]);
DEST[95:64] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[95:64]);
DEST[127:96] ← Convert_Integer_To_Single_Precision_Floating_Point(SRC[127:96]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTDQ2PS __m128 _mm_cvtepi32_ps(__m128i a)
SIMD Floating-Point Exceptions
Precision.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
0F 5B /r CVTDQ2PS xmm1,
xmm2/m128
Valid Valid Convert four packed signed
doubleword integers from
xmm2/m128 to four packed
single-precision floating-point
values in xmm1.