Intel 253666-024US - Manual (Page 256)

3-210 Vol. 2A CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to Packed Double-
word Integers
INSTRUCTION SET REFERENCE, A-M
CVTPS2DQ—Convert Packed Single-Precision Floating-Point Values to
Packed Doubleword Integers
Description
Converts four packed single-precision floating-point values in the source operand
(second operand) to four packed signed doubleword integers in the destination
operand (first operand).
The source operand can be an XMM register or a 128-bit memory location. The desti-
nation operand is an XMM register.
When a conversion is inexact, the value returned is rounded according to the
rounding control bits in the MXCSR register. If a converted result is larger than the
maximum signed doubleword integer, the floating-point invalid exception is raised,
and if this exception is masked, the indefinite integer value (80000000H) is returned.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).
Operation
DEST[31:0] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[31:0]);
DEST[63:32] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[63:32]);
DEST[95:64] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[95:64]);
DEST[127:96] ← Convert_Single_Precision_Floating_Point_To_Integer(SRC[127:96]);
Intel C/C++ Compiler Intrinsic Equivalent
CVTPS2DQ __m128i _mm_cvtps_epi32(__m128 a)
SIMD Floating-Point Exceptions
Invalid, Precision.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
If a memory operand is not aligned on a 16-byte boundary,
regardless of segment.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
66 0F 5B /r CVTPS2DQ xmm1,
xmm2/m128
Valid Valid Convert four packed single-precision
floating-point values from
xmm2/m128 to four packed signed
doubleword integers in xmm1.