Intel 253666-024US User Manual

Page 317

Vol. 2A 3-271

INSTRUCTION SET REFERENCE, A-M

DIVPS—Divide Packed Single-Precision Floating-Point Values

Description

Performs a SIMD divide of the four packed single-precision floating-point values in
the destination operand (first operand) by the four packed single-precision floating-
point values in the source operand (second operand), and stores the packed single-
precision floating-point results in the destination operand. The source operand can
be an XMM register or a 128-bit memory location. The destination operand is an XMM
register. See Chapter 10 in the Intel® 64 and IA-32 Architectures Software Devel-
oper’s Manual, Volume 1, for an overview of a SIMD single-precision floating-point
operation.
In 64-bit mode, use of the REX.R prefix permits this instruction to access additional
registers (XMM8-XMM15).

Operation

DEST[31:0] ← DEST[31:0]

(SRC[31:0]);

DEST[63:32] ← DEST[63:32]

(SRC[63:32]);

DEST[95:64] ← DEST[95:64]

(SRC[95:64]);

DEST[127:96] ← DEST[127:96]

(SRC[127:96]);

Intel C/C++ Compiler Intrinsic Equivalent

DIVPS

__m128 _mm_div_ps(__m128 a, __m128 b)

SIMD Floating-Point Exceptions

Overflow, Underflow, Invalid, Divide-by-Zero, Precision, Denormal.

Protected Mode Exceptions

#GP(0)

For an illegal memory operand effective address in the CS, DS,

ES, FS or GS segments.

If a memory operand is not aligned on a 16-byte boundary,

regardless of segment.

#SS(0)

For an illegal address in the SS segment.

#PF(fault-code)

For a page fault.

Opcode

Instruction

64-Bit

Mode

Compat/

Leg Mode

Description

0F 5E /r

DIVPS xmm1,

xmm2/m128

Valid

Divide packed single-precision floating-

point values in xmm1 by packed single-

precision floating-point values

xmm2/m128.