Intel 253666-024US - Manual (Page 88)

3-42 Vol. 2A ADDSS—Add Scalar Single-Precision Floating-Point Values
INSTRUCTION SET REFERENCE, A-M
ADDSS—Add Scalar Single-Precision Floating-Point Values
Description
Adds the low single-precision floating-point values from the source operand (second
operand) and the destination operand (first operand), and stores the single-precision
floating-point result in the destination operand.
The source operand can be an XMM register or a 32-bit memory location. The desti-
nation operand is an XMM register. The three high-order doublewords of the destina-
tion operand remain unchanged. See Chapter 10 in the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 1, for an overview of a scalar
single-precision floating-point operation.
In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to
access additional registers (XMM8-XMM15).
Operation
DEST[31:0] ← DEST[31:0] + SRC[31:0];
(* DEST[127:32] unchanged *)
Intel C/C++ Compiler Intrinsic Equivalent
ADDSS __m128 _mm_add_ss(__m128 a, __m128 b)
SIMD Floating-Point Exceptions
Overflow, Underflow, Invalid, Precision, Denormal.
Protected Mode Exceptions
#GP(0) For an illegal memory operand effective address in the CS, DS,
ES, FS or GS segments.
#SS(0) For an illegal address in the SS segment.
#PF(fault-code) For a page fault.
#NM If CRO.TS[bit 3] = 1.
#XM If an unmasked SIMD floating-point exception and CR4.OSXM-
MEXCPT[bit 10] = 1.
Opcode Instruction 64-Bit
Mode
Compat/
Leg Mode
Description
F3 0F 58 /r ADDSS xmm1, xmm2/m32 Valid Valid Add the low single-
precision floating-point
value from xmm2/m32 to
xmm1.