Intel 253666-024US - Manual (Page 663)

Vol. 2A 3-617
INSTRUCTION SET REFERENCE, A-M
MOVD/MOVQ—Move Doubleword/Move Quadword
Operation
MOVD instruction when destination operand is MMX technology register:
DEST[31:0] ← SRC;
DEST[63:32] ← 00000000H;
MOVD instruction when destination operand is XMM register:
DEST[31:0] ← SRC;
DEST[127:32] ← 000000000000000000000000H;
MOVD instruction when source operand is MMX technology or XMM register:
DEST ← SRC[31:0];
MOVQ instruction when destination operand is XMM register:
DEST[63:0] ← SRC[63:0];
DEST[127:64] ← 0000000000000000H;
MOVQ instruction when destination operand is r/m64:
DEST[63:0] ← SRC[63:0];
MOVQ instruction when source operand is XMM register or r/m64:
DEST ← SRC[63:0];
Intel C/C++ Compiler Intrinsic Equivalent
MOVD __m64 _mm_cvtsi32_si64 (int i )
MOVD int _mm_cvtsi64_si32 ( __m64m )
MOVD __m128i _mm_cvtsi32_si128 (int a)
MOVD int _mm_cvtsi128_si32 ( __m128i a)
Flags Affected
None.
SIMD Floating-Point Exceptions
None.
Protected Mode Exceptions
#GP(0) If the destination operand is in a non-writable segment.
If a memory operand effective address is outside the CS, DS,
ES, FS, or GS segment limit.
#SS(0) If a memory operand effective address is outside the SS
segment limit.