Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 86)

Functional Description
CPCI-6200 Installation and Use (6806800J66E) 86
4.3.4 I
2
C Bus 3
Bus 3 is connected between the IPMI controller and the following onboard I
2
C devices:
 ADT7461 temperature sensor
 64 KB user EEPROM
 64 KB FRU/SDR EEPROM
 64 KB SEL EEPROM used for system event log data
4.3.5 I
2
C Bus 4
Bus 4 is connected between the IPMI controller, processor, J5 connector and the following
onboard I
2
C devices:
 8 KB VPD EEPROM
 Two 64 KB EEPROM for user configuration data storage
 M41T83 Real Time Clock
 SPD EEPROMs of DDR3 (on DIMM modules)
The I
2
C interface is routed to the J5 connector to provide access to the serial EEPROM located
on the rear transition module.
4.3.6 I
2
C Bus 5
Bus 5 is connected between the IPMI controller and processor providing intercommunication
between the two. There is no onboard I
2
C device on this bus.
4.4 System Memory
The MPC8572 includes two memory controllers, which operate in asynchronous mode i.e., the
DDR3 clocks are derived from a separate external clock oscillator.
This board supports one bank of memory on each controller, using either 1 GB or 2 GB DDR3
SODIMM. This provides memory configurations of 2 and 4 GB. This board also supports
memory speeds of up to 400 MHz.