Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 205)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 205
8.4.13 NAND Flash Chip 2 Control Register
RB3 Ready/Busy 3
1 Device 3 is ready.
0 Device 3 is busy.
RB4 Ready/Busy 4
1 Device 4 is ready.
0 Device 4 is busy.
RSVD Reserved
Table 8-28 NAND Flash Chip 1 Status Register Field Definition (continued)
Table 8-29 NAND Flash Chip 2 Control Register, 0xF200_0014
Bit Field Operation Reset
7 CLE R/W 0
6 ALE R/W 0
5 WP R/W 1
4 RSVD R 0
3 RSVD R 0
2 RSVD R 0
1 RSVD R 0
0 RSVD R 0
Table 8-30 NAND Flash Chip 2 Control Register Field Definition
CLE Command Latch Enable
1 CLE is asserted when the device is accessed.
0 CLE is not asserted when the device is accessed.