Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 212)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 212
8.4.20 Watchdog Timer Control Register
Table 8-42 Watchdog Timer Control Register, 0xF200_0024
Bit Field Operation Reset
7 WDG_EN R/W 0
6 SYS_RST R/W 0
5 RSVD R 0
4 RSVD R 0
3 RSVD R 0
2 RSVD R 0
1 RSVD R 0
0 RSVD R 0
Table 8-43 Watchdog Timer Control Register Field Definition
WDG_EN Watch Dog Timer Enable
1 Watchdog timer is enabled.
0 Watchdog timer is disabled.
SYS_RST System Reset
1 Board and CPCI Backplane reset is generated when a time-
out occurs.
0 Board level reset is generated when a time out occurs.
RSVD Reserved