Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 216)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 216
8.4.24 PLD Date Code Register
This is a 32-bit register that contains the build date code of the timers/registers PLD.
8.4.25 Test Register 1
This is a 32-bit general purpose read/write register that is used by software for PLD test or
general status bit storage.
TEST_1— General purpose 32-bit R/W field
Table 8-49 PLD Date Code Register, 0xF200_0034
Bit Field Operation Reset
31:24 YEAR R XX
23:16 MONTH R XX
15:8 DATE R XX
7:0 DAY REV R XX
Table 8-50 PLD Date Code Register Field Definition
YEAR Four-digit year value of PLD's build date in decimal
MONTH Two-digit month value of PLD's build date in decimal
DATE Two-digit date value of PLD's build date in decimal
DAY REV Revision of the day
Table 8-51 Test Register 1, 0xF200_0038
Bit Field Operation Reset
31:0 TEST_1 R/W XX