Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 221)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 221
8.5 Interrupt Controller
The CPCI-6200 uses the MPC8572 integrated programmable interrupt controller (PIC) to
manage locally generated interrupts.The following table shows the external interrupting
devices and interrupt assignments along with corresponding edge/levels and polarities.
Refer to the MPC8572 reference manual for additional details regarding the operation of the
MPC8572 PIC.
Table 8-58 Interrupt Assignments
Interrupt Number Edge/Level Polarity Interrupt Source
0 Level Low PCI Express Port 1
1 Level Low PCI Express Port 1
2 Level Low PCI Express Port 1
3 Level Low PCI Express Port 1
4 Level Low PCI Express Port 2
5 Level Low PCI Express Port 2
6 Level Low PCI Express Port 2
7 Level Low PCI Express Port 2
8 Level Low PCI Express Expander
9 Level Low RTC, TEMP, Abort, IPMI, CPCI PLD
10 Level Low PHY’s
11 Level Low UARTs, External Timer 12
1. External timers are implemented in a PLD.
2. External UARTs are implemented using a DUART.