Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 220)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 220
The Tick Timer Counter is compared to the Compare Register. When they are equal, the tick
timer interrupt is asserted and the Overflow Counter is incremented. If the clear-on-compare
mode is enabled, the counter is also cleared. For periodic interrupts, this equation should be
used to calculate the compare register value for a specific period (T):
Compare register value = T (μs) x (1 / Reference clock frequency in MHz)
When programming the tick timer for periodic interrupts, the counter should be cleared to
zero by software and then enabled. If the counter does not initially start at 0, the time to the
first interrupt may be longer or shorter than expected. The rollover time for the counter is 71.6
minutes with the default 1 MHz reference clock.
8.4.27.4 Counter Registers
 Tick Timer 1 Counter Register—0xF202_0018 (32 bits)
 Tick Timer 2 Counter Register—0xF202_0028 (32 bits)
 Tick Timer 3 Counter Register—0xF202_0038 (32 bits)
 Tick Timer 4 Counter Register—0xF202_0048 (32 bits)
When enabled, the tick timer counter register increments with the reference clock value.
Software may read or write the counter at any time.
Table 8-57 Tick Timer Counter Register
Bit Field Operation Reset
31:0 Tick Timer Counter Value R/W 0