Figure 5-6, P2mx signal timings, Transition module preparation and installation – Artesyn CPCI-6200 Installation and Use (May 2015) User Manual
Page 129
Transition Module Preparation and Installation
CPCI-6200 Installation and Use (6806800J66E)
129
MXSYNC# is clocked out using the falling edge of MXCLK and MDXO is clocked out with the
rising edge of the MXCLK. MXDI is sampled at the rising edge of MXCLK (the CPCI-6115-
MCPTM synchronizes MXDI with MXCLK’s rising edge). The timing relationships among
MXCLK, MXSYNC#, MXDO, and MXDI are illustrated by the following figure:
Figure 5-6
P2MX Signal Timings
Serial Port Signal Descriptions
CTSn
clear to send
DCDn
data carrier detected
DSRn
data set ready
DTRn
data terminal ready
RIn
ring indicator
RTSn
request to send
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