Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 217)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 217
8.4.26 Test Register 2
This is a second 32-bit test register that reads back the complement of the data in Test Register
1.
TEST_2—A read from this address will return the complement of the data pattern in Test
Register 1. A write to this address will write the uncomplemented data to register TEST_1.
8.4.27 External Timer Registers
The CPCI-6200 provides a set of tick timer registers that is used to access four external timers
implemented in the PLD. These registers are 32-bit registers and are not byte writable.
8.4.27.1 Prescaler Register
The PRESCALE_ADJUST value is determined by the following formula:
Prescaler Adjust = 256 - (CLKIN/CLKOUT)
Where:
 CLKIN is the input clock source in MHz.
 CLKOUT is the desired output clock reference in MHz.
Table 8-52 Test Register 2, 0xF200_003C
Bit Field Operation Reset
31:0 TEST_2 R/W XX
Table 8-53 Prescaler Register, 0xE202_0000
Bit Field Operation Reset
31:8
7:0 PRESCALE_ADJUST R/W 0xE7