Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 60)

Controls, LEDs, and Connectors
CPCI-6200 Installation and Use (6806800J66E) 60
3.3.1 CPCI Bus Connector, J1
J1 is a five-row CPCI bus connector.
P6 Processor COP header
Planar header for processor COP emulation
P7 Planar header for debugging the PCI Express switch device
XJ1, XJ2 DDR3 DIMM 1 and 2 Socket
204-pin SO-UDIMM socket for DDR3 DIMM
S1 8-position switch
S2 8-position switch for IPMI functionality
Table 3-1 Onboard Connectors (continued)
Reference Designator Function
Table 3-2 CPCI Bus Connector Pinout, J1
Pin Row A Row B Row C Row D Row E
25 +5.0 V REQ64# ENUM# +3.3 V +5.0 V
24 AD[1] +5.0 V V(IO)1 AD[0] ACK64#
23 +3.3 V AD[4] AD[3] +5.0 V1 AD[2]
22 AD[7] GND +3.3 V1 AD[6] AD[5]
21 +3.3 V AD[9] AD[8] M66EN C/BE[0]#
20 AD[12] GND V(IO) AD[11] AD[10]
19 +3.3 V AD[15] AD[14] GND1 AD[13]
18 SERR# GND +3.3 V PAR C/BE[1]#
17 +3.3 V IPMB0_SCL IPMB0_SDA GND1 PERR#
16 DEVSEL# PCIXCAP V(IO) STOP# LOCK#
15 +3.3 V FRAME# IRDY# BD_SEL# TRDY#
KEY AREA (Pins 12 - 14)
11 AD[18] AD[17] AD[16] GND1 C/BE[2]#
10 AD[21] GND +3.3 V AD[20] AD[19]