Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 203)

Memory Maps and Addresses
CPCI-6200 Installation and Use (6806800J66E) 203
8.4.11 NAND Flash Chip 1 Presence Register
CE2 Chip Enable 2
1 CE2 is asserted when the device is accessed.
0 CE2 is not asserted when the device is accessed.
CE3 Chip Enable 3
1 CE3 is asserted when the device is accessed.
0 CE3 is not asserted when the device is accessed.
CE4 Chip Enable 1
1 CE4 is asserted when the device is accessed.
0 CE4 is not asserted when the device is accessed.
RSVD Reserved
Table 8-24 NAND Flash Chip 1 Select Register Field Definition (continued)
Table 8-25 NAND Flash Chip 1 Presence Register, 0xF200_0012
Bit Field Operation Reset
7 C1P R X
6 RSVD R 0
5 RSVD R 0
4 RSVD R 0
3 RSVD R 0
2 RSVD R 0
1 RSVD R 0
0 RSVD R 0