Artesyn CPCI-6200 Installation and Use (May 2015) - Manual (Page 106)

Functional Description
CPCI-6200 Installation and Use (6806800J66E) 106
4.19.1 Local Bus Control CPLD
This connects to the local bus controller of the processor. It provides access to boot flash,
NAND flash, MRAM, DUART and board registers. It also provides one watchdog timer, four tick
timers, and collects interrupts from various sources and routes them to processor. It operates
on a 25 MHz clock frequency.
4.19.2 Reset CPLD
This controls the reset function of the board. It generates reset for various board components
with varying timings. It also enables various power supplies. For more information, see
Reset
Control Logic .
4.19.3 CPCI Control CPLD
This complex programmable logic device (CPLD) configures the PLX PCI bridge device for
various operating modes. It controls PCI reset on back plane, enables CPCI signal terminations,
collects interrupts from CPCI sources (in system slot) and routes them to the local bus control
CPLD. It also controls the hot swap LED. For more information, see
Operation Modes .
4.19.4 Serial Multiplexer CPLD
This multiplexes the control lines of two serial port interfaces and routes them to the RTM
through the backplane. This allows fewer signals to be routed to the RTM thereby conserving
the total pin count requirement on J5 connector.
U84 EEPROM 512K, 8P SOIC IPMI, SEL Customer
Software For customer use
only
U12 Microcontroller, TQFP144 IPMI Controller ICT or through
P3 header
U83 EEPROM 512K, 8P SOIC IPMI FRU and SDR ICT or through
P3 header 0 to 1800 is address
for FRU data; above
1800 is SDR data
Table 4-6 Programming Devices (continued)
Reference
Designator
Description Function Pgm Method Remark