Altera MAX 10 Clocking and PLL - Manual (Page 9)

CLK
Pin GCLK
CLK6n
(1)
GCLK[16,17]
CLK7p
(1)
GCLK[16,18,19]
CLK7n
(1)
GCLK[15,18]
DPCLK0 GCLK[0,2]
DPCLK1 GCLK[1,3,4]
DPCLK2 GCLK[5,7]
DPCLK3 GCLK[6,8,9]
Figure 2-1: GCLK Network Sources for 10M02, 10M04, and 10M08 Devices
DPCLK2
DPCLK3
DPCLK0
DPCLK1
CLK[0,1][p,n] CLK[2,3][p,n]
GCLK[0..4] GCLK[5..9]
UG-M10CLKPLL
2015.05.04
Global Clock Network Sources 2-3
MAX 10 Clocking and PLL Architecture and Features Altera Corporation
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