Altera MAX 10 Clocking and PLL - Manual (Page 36)

Internal Oscillator Design Considerations
Guideline: Connectivity Restrictions
You cannot drive the PLLs with internal oscillator.
PLLs Design Considerations
Guideline: PLL Control Signals
You must include the
areset
signal in your designs if one of the following conditions is true:
• PLL reconfiguration or clock switchover is enabled in your design.
• Phase relationships between the PLL input clock and output clocks must be maintained after a loss-of-
lock condition.
• The input clock to the PLL is toggling or unstable at power-up.
• The
areset
signal is asserted after the input clock is stable and within specifications.
Related Information
PLL Control Signals on page 2-13
Guideline: Self-Reset
The lock time of a PLL is the amount of time required by the PLL to attain the target frequency and phase
relationship after device power-up, after a change in the PLL output frequency, or after resetting the PLL.
A PLL might lose lock for a number of reasons, such as the following causes:
• Excessive jitter on the input clock.
• Excessive switching noise on the clock inputs of the PLL.
• Excessive noise from the power supply, causing high output jitter and possible loss of lock.
• A glitch or stopping of the input clock to the PLL.
• Resetting the PLL by asserting the
areset
port of the PLL.
• An attempt to reconfigure the PLL might cause the
M
counter,
N
counter, or phase shift to change,
causing the PLL to lose lock. However, changes to the post-scale counters do not affect the PLL
locked
signal.
• PLL input clock frequency drifts outside the lock range specification.
• The PFD is disabled using the
pfdena
port. When this happens, the PLL output phase and frequency
tend to drift outside of the lock window.
The ALTPLL IP core allows you to monitor the PLL locking process using a lock signal named
locked
and also allows you to set the PLL to self-reset on loss of lock.
Guideline: Output Clocks
Each MAX 10 PLL supports up to five output clocks. You can use the output clock port as a core output
clock or an external output clock port. The core output clock feeds the FPGA core and the external output
clock feeds the dedicated pins on the FPGA.
3-2 Internal Oscillator Design Considerations
UG-M10CLKPLL
2015.05.04
Altera Corporation MAX 10 Clocking and PLL Design Considerations
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