Altera MAX 10 Clocking and PLL - Manual (Page 59)

Figure 4-13: IP Core Generated Files
Notes:
1. If supported and enabled for your IP variation
2. If functional simulation models are generated
3. Ignore this directory
<your_ip>.v or .vhd - Top-level IP synthesis file
_inst.v or .vhd - Sample instantiation template
.bsf - Block symbol schematic file
.vo or .vho - IP functional simulation model 2
_syn.v or .vhd - Timing & resource estimation netlist1
_bb.v - Verilog HDL black box EDA synthesis file
.qip - Quartus II IP integration file
greybox_tmp
3
.cmp - VHDL component declaration file
Obtaining the Resource Utilization Report
For details about the resource usage and performance of the ALTPLL_RECONFIG IP core, refer to the
compilation reports in the Quartus II software.
To view the compilation reports for the ALTPLL_RECONFIG IP core in the Quartus II software, follow
these steps:
1. On the Processing menu, click Start Compilation to run a full compilation.
2. After compiling the design, on the Processing menu, click Compilation Report.
3. In the Table of Contents browser, expand the Fitter folder by clicking the “+” icon.
4. Under Fitter, expand Resource section, and select Resource Usage Summary to view the resource
usage information.
5. Under Fitter, expand Resource section, and select Resource Utilization by Entity to view the
resource utilization information.
Internal Oscillator IP Core
The Internal Oscillator IP core specifies the internal oscillator frequencies for the devices.
UG-M10CLKPLL
2015.05.04
Obtaining the Resource Utilization Report 4-21
MAX 10 Clocking and PLL Implementation Guides Altera Corporation
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