Max 10 clocking and pll architecture and features, Clock networks architecture and features, Global clock networks – Altera MAX 10 Clocking and PLL User Manual
Page 7: Clock pins introduction, Clock networks architecture and features -1, Global clock networks -1, Clock pins introduction -1
MAX 10 Clocking and PLL Architecture and
Features
2
2015.05.04
UG-M10CLKPLL
Clock Networks Architecture and Features
Global Clock Networks
GCLKs drive throughout the entire device, feeding all device quadrants. All resources in the device, such
as the I/O elements, logic array blocks (LABs), dedicated multiplier blocks, and M9K memory blocks can
use GCLKs as clock sources. Use these clock network resources for control signals, such as clock enables
and clears fed by an external pin. Internal logic can also drive GCLKs for internally-generated GCLKs and
asynchronous clears, clock enables, or other control signals with high fan-out.
Clock Pins Introduction
There are two types of external clock pins that can drive the GCLK networks.
Dedicated Clock Input Pins
You can use the dedicated clock input pins (
CLK<#>[p,n]
) to drive clock and global signals, such as
asynchronous clears, presets, and clock enables for GCLK networks.
If you do not use the dedicated clock input pins for clock input, you can also use them as general-purpose
input or output pins.
The
CLK
pins can be single-ended or differential inputs. When you use the
CLK
pins as single-ended clock
inputs, both the
CLK<#>p
and
CLK<#>n
pins have dedicated connection to the GCLK networks. When you
use the
CLK
pins as differential inputs, pair two clock pins of the same number to receive differential
signaling.
Dual-Purpose Clock Pins
You can use the dual-purpose clock (
DPCLK
) pins for high fan-out control signals, such as protocol signals,
TRDY
and
IRDY
signals for PCI via GCLK networks.
The
DPCLK
pins are only available on the left and right of the I/O banks.
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