Altera MAX 10 Clocking and PLL - Manual (Page 66)

Port Name Condition Description
inclk[]
Required
Clock input of the clock buffer.
Input port
[1 DOWNTO 0]
wide.
You can specify up to two clock inputs,
inclk[1..0]
.
Clock pins, clock outputs from the PLL, and core signals can
drive the
inclk[]
port.
Multiple clock inputs are only supported for the global clock
networks.
Table 5-3: ALTCLKCTRL Output Ports for MAX 10 Devices
Port Name Condition Description
outclk
Required Output of the clock buffer.
Related Information
• Global Clock Control Block on page 2-4
• Global Clock Network Power Down on page 2-6
• Clock Enable Signals on page 2-7
• Guideline: Clock Enable Signals on page 3-1
UG-M10CLKPLL
2015.05.04
ALTCLKCTRL Ports and Signals 5-3
ALTCLKCTRL IP Core References Altera Corporation
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