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Altclkctrl ip core references, Altclkctrl parameters, Altclkctrl ip core references -1 – Altera MAX 10 Clocking and PLL User Manual

Page 64: Altclkctrl parameters -1

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ALTCLKCTRL IP Core References

5

2015.05.04

UG-M10CLKPLL

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ALTCLKCTRL Parameters

Table 5-1: ALTCLKCTRL IP Core Parameters for MAX 10 Devices

This table lists the IP core parameters applicable to MAX 10 devices.

Parameter

Value

Decription

How do you want to use

the ALTCLKCTRL

For global clock, or

For external path

Specify the ALTCLKCTRL buffering mode. You can

select from the following modes:
For global clock—Allows a clock signal to reach all

parts of the chip with the same amount of skew; you

can select input port

clkselect

to switch between

the four clock inputs.

For external path—Represents the clock path from

the outputs of the PLL to the dedicated clock output

pins; only one clock output is accepted.

How many clock inputs

would you like?

1, 2, 3, or 4

Specify the number of input clock sources for the clock

control block. You can specify up to four clock inputs.
You can change the number of clock inputs only if you

choose For global clock option.

Create ‘ena’ port to

enable or disable the

clock network driven by

this buffer

On or Off

Turn on this option if you want to create an active high

clock enable signal to enable or disable the clock

network.

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