Altera MAX 10 Clocking and PLL User Manual
Page 15
Phase-Frequency Detector (PFD)
The PFD has inputs from the feedback clock, f
FB
, and the input reference clock, f
REF
. The PLL compares
the rising edge of the input reference clock to a feedback clock using a PFD. The PFD produces an up or
down signal that determines whether the VCO needs to operate at a higher or lower frequency.
Charge Pump (CP)
If the charge pump receives a logic high on the up signal, current is driven into the loop filter. If the
charge pump receives a logic high on the down signal, current is drawn from the loop filter.
Loop Filter (LF)
The loop filter converts the up and down signals from the PFD to a voltage that is used to bias the VCO.
The loop filter filters out glitches from the charge pump and prevents voltage overshoot, which minimizes
jitter on the VCO.
Voltage-Controlled Oscillator (VCO)
The voltage from the charge pump determines how fast the VCO operates. The VCO is implemented as a
four-stage differential ring oscillator. A divide counter,
M
, is inserted in the feedback loop to increase the
VCO frequency, f
VCO
, above the input reference frequency, f
REF
.
The VCO frequency is determined using the following equation:
f
VCO
= f
REF
×
M
= f
IN
×
M
/
N
,
where f
IN
is the input clock frequency to the PLL and
N
is the pre-scale counter.
The VCO frequency is a critical parameter that must be between 600 and 1,300 MHz to ensure proper
operation of the PLL. The Quartus II software automatically sets the VCO frequency within the
recommended range based on the clock output and phase shift requirements in your design.
Post-Scale Counters (
C
)
The VCO output can feed up to five post-scale counters (
C0
,
C1
,
C2
,
C3
, and
C4
). These post-scale counters
allow the PLL to produce a number of harmonically-related frequencies.
Internal Delay Elements
The MAX 10 PLLs have internal delay elements to compensate for routing on the GCLK networks and
I/O buffers. These internal delays are fixed.
PLL Outputs
The MAX 10 PLL supports up to 5 GCLK outputs and 1 dedicated external clock output. The output
frequency, f
OUT
, to the GCLK network or dedicated external clock output is determined using the
following equation:
f
REF
= f
IN
/
N
and
f
OUT
= f
VCO
/
C
= (f
REF
×
M
)/
C
= (f
IN
×
M
)/(
N
×
C
),
where
C
is the setting on the
C0
,
C1
,
C2
,
C3
, or
C4
counter.
UG-M10CLKPLL
2015.05.04
PLL Architecture
2-9
MAX 10 Clocking and PLL Architecture and Features
Altera Corporation