Altera MAX 10 Clocking and PLL User Manual
Page 80
Port Name
Condition
Description
read_param
Optional
Reads the parameter specified with the
counter_type
and
counter_param
ports from cache and fed to the
data_
out[]
port.
When asserted, the
read_param
signal indicates that the
scan cache should be read and fed to
data_out[]
. The bit
location of the scan cache and the number of bits read
and sent to
data_out[]
depend on the
counter_type
and
counter_param
values. The
read_param
signal is
sampled at the rising clock edge. If the
read_param
signal
is asserted, the parameter value is read from the cache.
Assert the
read_param
signal for 1 clock cycle only to
prevent the parameter from being read twice.
The
busy
signal is asserted on the rising clock edge
following the assertion of the
read_param
signal. While
the parameter is read, the
busy
signal remains asserted.
After the
busy
signal is deasserted, the value on
data_
out[]
is valid and the next parameter can be loaded.
While the
busy
signal is asserted, the value on
data_
out[]
is not valid.
When the
read_param
signal is asserted, the
busy
signal is
only asserted on the following rising edge of the clock and
not on the same clock cycle as the
read_param
signal.
write_param
Optional
Writes the parameter specified with the
counter_type
and
counter_param
ports to the cache with the value
specified on the
data_in[]
port.
When asserted, the
write_param
signal indicates that the
value on
data_in[]
should be written to the parameter
specified by
counter_type[]
and
counter_param[]
. The
number of bits read from the
data_in[]
port depends on
the parameter. The
write_param
signal is sampled at the
rising clock edge. If the
write_param
signal is asserted,
the parameter value is written to the cache. Assert the
write_param
signal for 1 clock cycle only to prevent the
parameter from being written twice.
The
busy
signal is asserted on the rising clock edge
following the assertion of the
write_param
signal. While
the parameter is being written, the
busy
signal remains
asserted and input to
data_in[]
is ignored. After the
busy
signal is deasserted, the next parameter can be
written.
When the
write_param
signal is asserted, the
busy
signal
is only asserted on the following rising edge of the clock.
The
busy
signal is not asserted on the same clock cycle as
the
write_param
signal.
7-4
ALTPLL_RECONFIG Ports and Signals
UG-M10CLKPLL
2015.05.04
Altera Corporation
ALTPLL_RECONFIG IP Core References