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Altera MAX 10 Clocking and PLL User Manual

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Contents

MAX 10 Clocking and PLL Overview................................................................. 1-1

Clock Networks Overview.......................................................................................................................... 1-1

Internal Oscillator Overview......................................................................................................................1-1

PLLs Overview..............................................................................................................................................1-1

MAX 10 Clocking and PLL Architecture and Features......................................2-1

Clock Networks Architecture and Features............................................................................................. 2-1

Global Clock Networks................................................................................................................... 2-1

Clock Pins Introduction..................................................................................................................2-1

Clock Resources............................................................................................................................... 2-2

Global Clock Network Sources...................................................................................................... 2-2

Global Clock Control Block............................................................................................................2-4

Global Clock Network Power Down.............................................................................................2-6

Clock Enable Signals........................................................................................................................2-7

Internal Oscillator Architecture and Features......................................................................................... 2-8

PLLs Architecture and Features.................................................................................................................2-8

PLL Architecture..............................................................................................................................2-8

PLL Features................................................................................................................................... 2-10

PLL Locations.................................................................................................................................2-10

Clock Pin to PLL Connections.....................................................................................................2-12

PLL Counter to GCLK Connections...........................................................................................2-12

PLL Control Signals.......................................................................................................................2-13

Clock Feedback Modes..................................................................................................................2-14

PLL External Clock Output.......................................................................................................... 2-17

ADC Clock Input from PLL.........................................................................................................2-19

Spread-Spectrum Clocking...........................................................................................................2-19

PLL Programmable Parameters...................................................................................................2-19

Clock Switchover........................................................................................................................... 2-22

PLL Cascading................................................................................................................................2-26

PLL Reconfiguration..................................................................................................................... 2-26

MAX 10 Clocking and PLL Design Considerations........................................... 3-1

Clock Networks Design Considerations...................................................................................................3-1

Guideline: Clock Enable Signals.................................................................................................... 3-1

Guideline: Connectivity Restrictions............................................................................................ 3-1

Internal Oscillator Design Considerations...............................................................................................3-2

Guideline: Connectivity Restrictions............................................................................................ 3-2

PLLs Design Considerations...................................................................................................................... 3-2

Guideline: PLL Control Signals......................................................................................................3-2

Guideline: Self-Reset........................................................................................................................3-2

Guideline: Output Clocks............................................................................................................... 3-2

TOC-2

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