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Programmable bandwidth with advanced parameters, Pll dynamic reconfiguration implementation – Altera MAX 10 Clocking and PLL User Manual

Page 48

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Programmable Bandwidth with Advanced Parameters

An advanced level of control is also possible for precise control of the PLL loop filter characteristics. This

level allows you to explicitly select the following advanced parameters:
• Charge pump current (

charge_pump_current

)

• Loop filter resistance (

loop_filter_r

)

• Loop filter capacitance(

loop_filter_c

)

This option is intended for advanced users who know the exact details of their PLL configuration. You

can use this option if you understand the parameters well enough to set them optimally. The files

generated are not intended to be reused by the ALTPLL IP core parameter editor. After the ALTPLL IP

core output files are specified using the advanced parameters, the Quartus II compiler cannot change

them. For example, the compiler cannot perform optimization. Thus, your design cannot benefit from

improved algorithms of the compiler. The Quartus II compiler cannot select better settings or change

some settings that the ALTPLL IP core parameter editor finds to be incompatible with your design.
The parameter settings to generate output files using advanced PLL parameters are located on the Inputs/

Lock page of the ALTPLL IP core parameter editor.
Turn on Create output file(s) using the 'Advanced' PLL parameters to enable the feature.
When you turn on this option, the generated output files contain all of the initial counter values used in

the PLL. You can use these values for functional simulation in a third-party simulator.
These parameter settings create no additional top-level ports.

Related Information

Programmable Bandwidth

on page 2-19

Charge Pump and Loop Filter

on page 4-13

Provides more information about the PLL components to update PLL bandwidth in real time.

Programmable Bandwidth Parameter Settings

on page 6-2

PLL Dynamic Reconfiguration Implementation

To reconfigure the PLL counters, perform the following steps:
1. Assert the

scanclkena

signal at least one

scanclk

cycle prior to shifting in the first bit of

scandata

(

Dn

).

2. Shift the serial data (

scandata

) into the scan chain on the second rising edge of

scanclk

.

3. After all 144 bits have been scanned into the scan chain, deassert the

scanclkena

signal to prevent

inadvertent shifting of bits in the scan chain.

4. Assert the

configupdate

signal for one

scanclk

cycle to update the PLL counters with the contents of

the scan chain.

The

scandone

signal goes high indicating that the PLL is being reconfigured. A falling edge indicates

that the PLL counters have been updated with new settings.

5. Reset the PLL using the

areset

signal if you make any changes to the

M

,

N

, post-scale output

C

counters, or the I

CP

, R, and C settings.

6. You can repeat steps 1 through 5 to reconfigure the PLL any number of times.

4-10

Programmable Bandwidth with Advanced Parameters

UG-M10CLKPLL

2015.05.04

Altera Corporation

MAX 10 Clocking and PLL Implementation Guides

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