Max 10 clocking and pll design considerations, Clock networks design considerations, Guideline: clock enable signals – Altera MAX 10 Clocking and PLL User Manual
Page 35: Guideline: connectivity restrictions, Max 10 clocking and pll design considerations -1, Clock networks design considerations -1, Guideline: clock enable signals -1, Guideline: connectivity restrictions -1
MAX 10 Clocking and PLL Design
Considerations
3
2015.05.04
UG-M10CLKPLL
Clock Networks Design Considerations
Guideline: Clock Enable Signals
Altera recommends using the
clkena
signals when switching the clock source to the PLLs or GCLK. The
recommended sequence is as follows:
1. Disable the primary output clock by deasserting the
clkena
signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control block.
3. Allow some clock cycles of the secondary clock to pass before reasserting the
clkena
signal. The exact
number of clock cycles to wait before enabling the secondary clock depends on your design. You can
build a custom logic to ensure a glitch-free transition when switching between different clock sources.
Related Information
•
on page 2-7
•
on page 5-1
•
on page 5-2
Guideline: Connectivity Restrictions
The following guidelines describe the restrictions associated with the signal sources that can drive the
inclk
input:
• You must use the
inclk
ports that are consistent with the
clkselect
ports.
• When you are using multiple input sources, the
inclk
ports can only be driven by the dedicated clock
input pins and the PLL clock outputs.
• If the clock control block feeds any
inclk
port of another clock control block, both clock control
blocks must be able to be reduced to a single clock control block of equivalent functionality.
• When you are using the glitch-free switchover feature, the clock you are switching from must be active.
If the clock is not active, the switchover circuit cannot transition from the clock you originally selected.
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