Adc clock input from pll, Spread-spectrum clocking, Pll programmable parameters – Altera MAX 10 Clocking and PLL User Manual
Page 25: Programmable duty cycle, Programmable bandwidth, Adc clock input from pll -19, Spread-spectrum clocking -19, Pll programmable parameters -19
ADC Clock Input from PLL
Only the
C0
output counter from
PLL1
and
PLL3
can drive the ADC clock.
Counter
C0
has dedicated path to the ADC clock input.
Spread-Spectrum Clocking
The MAX 10 devices allow a spread-spectrum input with typical modulation frequencies. However, the
device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal
looks like deterministic jitter at the input of the PLL.
The MAX 10 PLLs can track a spread-spectrum input clock if the input signal meets the following
conditions:
• The input signal is within the input jitter tolerance specifications.
• The modulation frequency of the input clock is below the PLL bandwidth as specified in the Fitter
report.
MAX 10 devices cannot generate spread-spectrum signals internally.
PLL Programmable Parameters
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This
feature is supported on the PLL post-scale counters.
The duty cycle setting is achieved by a low and high time-count setting for the post-scale counters. To
determine the duty cycle choices, the Quartus II software uses the frequency input and the required
multiply or divide rate.
The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50%
divided by the post-scale counter value. For example, if the
C0
counter is 10, steps of 5% are possible for
duty cycle choices between 5 to 90%.
Combining the programmable duty cycle with programmable phase shift allows the generation of precise
nonoverlapping clocks.
Related Information
Post-Scale Counters (C0 to C4)
Provides more information about configuring the duty cycle of the post-scale counters in real time.
Programmable Bandwidth
The PLL bandwidth is the measure of the PLL’s ability to track the input clock and its associated jitter.
The MAX 10 PLLs provide advanced control of the PLL bandwidth using the programmable characteris‐
tics of the PLL loop, including loop filter and charge pump. The 3-dB frequency of the closed-loop gain in
the PLL determines the PLL bandwidth. The bandwidth is approximately the unity gain point for open
loop PLL response.
Related Information
•
Programmable Bandwidth with Advanced Parameters
UG-M10CLKPLL
2015.05.04
ADC Clock Input from PLL
2-19
MAX 10 Clocking and PLL Architecture and Features
Altera Corporation