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Internal oscillator ip core references, Internal oscillator parameters, Internal oscillator ports and signals – Altera MAX 10 Clocking and PLL User Manual

Page 85: Internal oscillator ip core references -1, Internal oscillator parameters -1, Internal oscillator ports and signals -1

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Internal Oscillator IP Core References

8

2015.05.04

UG-M10CLKPLL

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Internal Oscillator Parameters

Table 8-1: Internal Oscillator IP Core Parameters for MAX 10 Devices

This table lists the IP core parameters applicable to MAX 10 devices.

Parameter

Value

Decription

Clock Frequency

55, 116

Specify the clock frequency for simulation. If not

specified, the default value is 55 MHz.

Internal Oscillator Ports and Signals

Table 8-2: Internal Oscillator Input Port for MAX 10 Devices

Port Name

Condition

Description

oscena

Required

Input control signal to turn on or turn off the internal

oscillator.

Table 8-3: Internal Oscillator Output Port for MAX 10 Devices

Port Name

Condition

Description

clkout

Optional

Output clock from the internal oscillator.

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