Max 10 clocking and pll overview, Clock networks overview, Internal oscillator overview – Altera MAX 10 Clocking and PLL User Manual
Page 5: Plls overview, Max 10 clocking and pll overview -1, Clock networks overview -1, Internal oscillator overview -1, Plls overview -1
MAX 10 Clocking and PLL Overview
1
2015.05.04
UG-M10CLKPLL
Clock Networks Overview
MAX
®
10 devices support global clock (GCLK) networks.
Clock networks provide clock sources for the core. You can use clock networks in high fan-out global
signal network such as reset and clear.
Internal Oscillator Overview
MAX 10 devices offer built-in internal oscillator up to 116 MHz.
You can enable or disable the internal oscillator.
PLLs Overview
Phase-locked loops (PLLs) provide robust clock management and synthesis for device clock management,
external system clock management, and I/O interface clocking.
You can use the PLLs as follows:
• Zero-delay buffer
• Jitter attenuator
• Low-skew fan-out buffer
• Frequency synthesizer
• Reduce the number of oscillators required on the board
• Reduce the clock pins used in the device by synthesizing multiple clock frequencies from a single
reference clock source
• On-chip clock de-skew
• Dynamic phase shift
• Counters reconfiguration
• Bandwidth reconfiguration
• Programmable output duty cycle
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