Max 10 clocking and pll implementation guides, Altclkctrl ip core, Ip catalog and parameter editor – Altera MAX 10 Clocking and PLL User Manual
Page 39: Max 10 clocking and pll implementation guides -1, Altclkctrl ip core -1, Ip catalog and parameter editor -1
MAX 10 Clocking and PLL Implementation
Guides
4
2015.05.04
UG-M10CLKPLL
ALTCLKCTRL IP Core
The clock control block (ALTCLKCTRL) IP core is a clock control function for configuring the clock
control block.
The common applications of the ALTCLKCTRL IP core are as follows:
• Dynamic clock source selection—When using the clock control block, you can select the dynamic
clock source that drives the global clock network.
• Dynamic power-down of a clock network—The dynamic clock enable or disable feature allows
internal logic to power down the clock network. When a clock network is powered down, all the logic
fed by that clock network is not toggling, thus reducing the overall power consumption of the device.
The ALTCLKCTRL IP core provides the following features:
• Supports clock control block operation mode specifications
• Supports specification of the number of input clock sources
• Provides an active high clock enable control input
IP Catalog and Parameter Editor
The Quartus II IP Catalog (Tools > IP Catalog) and parameter editor help you easily customize and
integrate IP cores into your project. You can use the IP Catalog and parameter editor to select, customize,
and generate files representing your custom IP variation.
Note: The IP Catalog (Tools > IP Catalog) and parameter editor replace the MegaWizard
™
Plug-In
Manager for IP selection and parameterization, beginning in Quartus II software version 14.0. Use
the IP Catalog and parameter editor to locate and paramaterize Altera IP cores.
The IP Catalog lists installed IP cores available for your design. Double-click any IP core to launch the
parameter editor and generate files representing your IP variation. The parameter editor prompts you to
specify an IP variation name, optional ports, and output file generation options. The parameter editor
generates a top-level Qsys system file (
.qsys
) or Quartus II IP file (
.qip
) representing the IP core in your
project. You can also parameterize an IP variation without an open project.
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