Altera MAX 10 Clocking and PLL User Manual
Page 82
Table 7-3: ALTPLL_RECONFIG Output Ports for MAX 10 Devices
Port Name
Condition
Description
data_out[]
Optional
Data read from the cache when
read_param
is asserted.
This 9-bit output bus provides the parameter data to the
user. When the
read_param
signal is asserted, the values
on
counter_type[]
and
counter_param[]
determine the
parameter value that is loaded from cache and driven on
the
data_out[]
bus. When the IP core deasserts the
busy
signal, the appropriate bits of the bus (for example,
[0]
or
[3..0]
) hold a valid value.
busy
Optional
Indicates that the PLL is reading or writing a parameter to
the cache, or is configuring the PLL.
While the
busy
signal is asserted, no parameters can be
read or written, and no reconfiguration can be initiated.
Changes to the IP core can be made only when the
busy
signal is not asserted. The signal goes high when the
read_param
,
write_param
, or
reconfig
input port is
asserted, and remains high until the specified operation is
complete. In the case of a reconfiguration operation, the
busy
signal remains high until the
pll_areset
signal is
asserted and then deasserted.
pll_areset
Required
Drives the
areset
port on the PLL to be reconfigured.
The
pll_areset
port must be connected to the
areset
port of the ALTPLL IP core for the reconfiguration to
function correctly. This signal is active high. The
pll_
areset
is asserted when
pll_areset_in
is asserted, or,
after reconfiguration, at the next rising clock edge after
the
scandone
signal goes high. If you use the ALTPLL_
RECONFIG IP core, use the
pll_areset
output port to
drive the PLL
areset
port.
pll_configupdate
Optional
Drives the
configupdate
port on the PLL to be reconfig‐
ured. When asserted, the
pll_configupdate
port loads
selected data to PLL configuration latches. The signal is
asserted after the final data bit is sent out.
pll_scanclk
Required
Drives the
scanclk
port on the PLL to be reconfigured.
For information about the maximum
scanclk
frequency
for the various devices, refer to the respective device
handbook.
7-6
ALTPLL_RECONFIG Ports and Signals
UG-M10CLKPLL
2015.05.04
Altera Corporation
ALTPLL_RECONFIG IP Core References