Altera MAX 10 Clocking and PLL User Manual
Page 86
Additonal Information for MAX 10 Clocking
and PLL User Guide
A
2015.05.04
UG-M10CLKPLL
Document Revision History for MAX 10 Clocking and PLL User Guide
Date
Version
Changes
May 2015
2015.05.04 Rearranged the fine resolution phase shift equation.
December 2014
2014.12.15 • Corrected the statement that if you do not use the dedicated clock
input pins for clock input, you can also use them as general-
purpose input or output pins.
• Added description in Internal Oscillator Architecture and Features
to state that the internal ring oscillator operates up to 232 MHz and
this frequency is not accessible.
• Added connectivity restrictions guideline for internal oscillator.
• Added Internal Oscillator IP Core parameter: Clock Frequency.
• Moved Internal Oscillator Frequencies table from Internal
Oscillator Architecture and Features chapter to MAX 10 FPGA
Device Datasheet.
September 2014
2014.09.22 Initial release.
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