Maxim Integrated DS4830A Optical Microcontroller User Manual

Page 99

DS4830A User’s Guide

• Sets the I2CST_S.I2CTXI flag to indicate that the I

C slave controller has transmitted a byte. This can

generate an interrupt if enabled.

• Sets or clears the I2CST_S.I2CNACKI flag to reflect the received acknowledge bit. The setting of I2CNACKI

can generate an interrupt if enabled.

• Clears the I2CST_S.I2CBUSY flag to indicate that the I

C slave controller is not actively participating in the

transfer of data.

The detection of an ACK by the I

C slave controller indicates that the host wants to receive another byte of data.

The I

C slave controller maintains control of SDA following the ACK. The next byte to transmit needs to be loaded

into I2CBUF_S prior to the host starting to clock this next byte.

The detection of a NACK indicates that the host does not want to receive any additional data. The I

C slave

controller releases control of SDA following the reception of NACK bit. After the NACK, the slave controller enters
idle state and monitors the I

C bus for a START or STOP condition.

11.1.7.2 – Advanced Mode Data Transmission
To achieve 400kHz I

C without clock stretch, the DS4830A I

C Controller has 4-word TX Pages for each slave

address. The TXPG_EN bit in the I2CTXFIE register enables the TX PAGEs of the all enabled slave addresses. The
user should pre-fill these 4-word pages to ensure data is available to transmit immedialty following a slave address
match. When data is being transmit, the I

C controller automatically selects one of the four TX Pages depending

upon which SLA [3:0] bits are set during the slave address match event.

The individual TX page should be written in the word mode using the I2CBUF_S. See below pseudo code to write
the TX page of I2CSLA2_S address

MOVE DP[0], #01Ch

//DP[0] in word mode

MOVE M2[21], #00F2h

//Select TX PAGE2 in CUR_SLA

MOVE RPNTR, #0000h

//Initialize RPNTR to current read address. When written to 0000h,

//RPNTR will populate with the correct SRAM memory location for

//read data

//Copy word 1

MOVE DP[0], RPNTR

//Copy current memory address to the data pointer

MOVE M2[0], @DP[0]

//Copy data from @DP[0] to I2CBUF_S register (M2[0])

//I2CBUF_S will load data into TX PAGE

// RPNTR = RPNTR + 1 automatically when data is loaded
//into I2CBUF_S. Rollover handled internally.

//Copy word 2

MOVE DP[0], RPNTR

//Copy current memory address in the data pointer

MOVE M2[0], @DP[0]

//Copy data from @DP[0] to TX PAGE via I2CBUF_S register

//Copy word 3

MOVE DP[0], RPNTR

//Copy current memory address in the data pointer

MOVE M2[0], @DP[0]

//Copy data from @DP[0] to TX PAGE via I2CBUF_S register

//Copy word 4

MOVE DP[0], RPNTR

//Copy current memory address in the data pointer

MOVE M2[0], @DP[0]

// Copy data from @DP[0] to TX PAGE via I2CBUF_S register

When TX page is enabled, the SLA[3:0] bits in the CUR_SLA register selects one of the TX pages as shown in
Figure 11-3. The I

C controller reads data from the selected TX page and writes to the shift register. When the I

controller is transmitting data, the threshold interrupt flag (THSH) in the I2CTXST register will be set when there are
4 bytes are remaining. This can generate an interrupt, if enabled.