Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 122)

DS4830A User’s Guide
122
13.1.1.1 – Write Mode (RWN=0)
The 3-Wire master generates 16 clock cycles on MCL pin. It outputs 16-bits (MSB first DADDR data) to the MDIO
line at the falling edge of the MCL. After completion of 16 clocks, the 3-Wire BUSY flag is cleared and the data
transfer complete flag TWI is set to ‘1’ which generates interrupt if enabled. The master closes the transmission by
setting the MCS to ‘0’.
13.1.1.2 – Read Mode (RWN=1)
The 3-Wire master generates 16 clock cycles at MCL. It outputs 8-bits of ADDR + RWN (MSB first) to the MDIO line
at the falling edge of the clocks. The MDIO line is released after the RWN bit is transmitted. The slave outputs 8-bits
of data (MSB first) at rising edge of the clock. The master reads the data bits at the falling edge of the clocks. After
the completion of 16 clocks, the 3-Wire BUSY flag is cleared and the data transfer complete flag TWI is set to ‘1’
which generates interrupt if enabled. Read data is available in the DADDR [7:0] bits and the DADDR[8:15] bits set to
0.The master closes the transmission by setting the MCS to ‘0’.
13.1.1.3 – Chip Select Disable Mode (TWCDIS = 1)
The DS4830A 3-Wire master provides facility to disable MCS chip select. In this mode, any GPIO can be configured
to function as chip select and the 3-Wire interface does not control MCS during the communication. In chip select
disabled mode, the application program should control chip select during the 3-Wire communication. Using this
feature, multiple 3-Wire slaves can be interfaced with the 3-Wire master.