Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 30)

DS4830A User’s Guide
30
3.11 – Instruction Pointer Register (IP, 0Ch[00h])
Initialization: This register is cleared to 8000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:0
This register contains the address of the next instruction to be executed and is automatically
incremented by 1 after each program fetch. Writing an address value to this register will cause
program flow to jump to that address. Reading from this register will not affect program flow.
3.12 – Stack Pointer Register (SP, 0Dh[01h])
Initialization: This register is cleared to 001Fh on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:4 Reserved; all reads return 0.
4:0
These four bits indicate the current top of the hardware stack, from 0h to 1Fh. This pointer is
incremented after a value is pushed on the stack and decremented before a value is popped from
the stack.
3.13 – Interrupt Vector Register (IV, 0Dh[02h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:0
This register contains the address of the interrupt service routine. The interrupt handler will
generate a CALL to this address whenever an interrupt is acknowledged.
3.14 – Loop Counter 0 Register (LC[0], 0Dh[06h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:0
This register is used as the loop counter for the DJNZ LC[0], src operation. This operation
decrements LC[0] by one and then jumps to the address specified in the instruction by src if LC[0]
= 0.
3.15 – Loop Counter 1 Register (LC[1], 0Dh[07h])
Initialization: This register is cleared to 0000h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
15:0
This register is used as the loop counter for the DJNZ LC[1], src operation. This operation
decrements LC[1] by one and then jumps to the address specified in the instruction by src if LC[1]
= 0.
3.16 – Frame Pointer Offset Register (OFFS, 0Eh[03h])
Initialization: This register is cleared to 00h on all forms of reset.
Access: Unrestricted direct read/write access.
BIT DESCRIPTION
7:0
This 8-bit register provides the Frame Pointer (FP) offset from the base pointer (BP). The Frame
Pointer is formed by unsigned addition of Frame Pointer Base Register (BP) and Frame Pointer
Offset Register (Offs). The contents of this register can be post-incremented or post-decremented
when using the Frame Pointer for read operations and may be pre-incremented or pre-
decremented when using the Frame Pointer for write operations. A carry out or borrow resulting
from an increment/decrement operation has no effect on the Frame Pointer Base Register (BP).