Ds4830a user’s guide – Maxim Integrated DS4830A Optical Microcontroller User Manual
Page 80
DS4830A User’s Guide
80
9.2.5 Low Trip Interrupt High Register (LTIH)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
IE[15:8]
IF[15:8]
Reset
Access
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BIT
NAME
DESCRIPTION
15:8
IE[15:8]
Low Trip Interrupt Enable. This register is used to enable/mask the corresponding
LTIH register interrupts for upper 8 comparisions. For example, if LTIH = 0x0100 then
Quick Trip list 8 can generate an interrupt when LTIH LSB is set to ‘1’ and all other
interrupts from LTIH are ignored. Similarly, if LTIH = 0xFF00, then all 8 flags from LTIH
generate interrupts.
7:0
IF[15:8]
Low Trip Interrupt Flag. The corresponding bit of the low trip interrupt register is set
when a low threshold trip is occurred on a channel list register. In other words, when
voltage across channel is less than the low threshold configuration for the channel.
For example, if a low trip occurs on the list register 8 then LTHI is set to 0x0001. If the
corresponding IE bit is also ‘1’, and then this generates an interrupt. Software should
clear the Low Trip Interrupt Flag once it is set by hardware. Setting this bit to ‘1’ by
software generates an interrupt if enabled.
9.2.6 High Trip Interrupt High Register (HTIH)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
IE[15:8]
IF[15:8]
Reset
Access
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:8
IE[15:8]
High Trip Interrupt Enable. This register is used to enable/mask the corresponding
HTIH register interrupts for the upper 8 comparisons. For Example, if HTIH = 0x0100
then Quick Trip list 8 can generate an interrupt when HTIH LSB is set to ‘1’ and all
other interrupts from HTIH are ignored. Similarly, if HTIH = 0xFF00, then all 8 flags
from HTIH generate interrupts.
7:0
IF[15:8]
High Trip Interrupt Flag. The corresponding bit of the High Trip Interrupt register is
set when a high threshold trip is occurred on a channel list register. In other words,
when voltage across channel is more than the high threshold configuration for the
channel.
For example, if a high trip occurs on the list register 8 then HTIH is set to 0x0001. If
the corresponding IE bit is also ‘1’, and then this generates an interrupt. Software
should clear the High Trip Interrupt Flag once it is set by hardware. Setting this bit to
‘1’ by software generates an interrupt if enabled.
9.2.7 – Quick Trip List Register (QTLST)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
-
-
-
-
QTSTART[3:0]
-
-
-
-
QTEND[3:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
r
r
r
r
rw
rw
rw
rw
r
r
r
r
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:12
-
Reserved. The user should write these bits to ‘0’.
11:8
QTSTART[3:0] Quick Trip Configuration Start Address Bits [3:0]. These bits select the start
address of quick trip channel list.
7:4
-
Reserved. The user should write these bits to ‘0’.
3:0
QTEND[3:0]
Quick Trip Configuration Ending Address Bits [3:0]. These bits select the stop
address of quick trip channel list.