Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 57)

DS4830A User’s Guide
57
7.2.2 – ADC Status Register (ADST)
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name - - - - ENALE_2X - - - ADCAVG ADCONV ADCFG ADIDX[4:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access r r r r rw r r r rw rw rw rw rw rw rw rw
BIT NAME DESCRIPTION
15:12 - Reserved. The user should not write to these bits.
11 ENABLE_2X ADC Fast Conversion Mode. When ADST.ENABLE_2X = 1, the ADC operates in the
fast mode. If reset to 0, normal conversion mode is used.
7 ADCAVG ADC Average Configuration Register Select.
When ADCAVG = 1 and ADCFG = 0, the ADDATA register points to the ADC Channel
averaging configuration registers which allow configuration of averaging for each ADC
channel. See 7.2.6.2 for ADC sample average configurations.
6 ADCONV ADC Start Conversion. Setting this bit to ‘1’ starts the ADC conversion process. This
bit remains set until the ADC conversion process is finished. In single sequence mode,
this bit is cleared to ‘0’ when the ADC conversion sequence is finished. In continuous
sequence mode, this bit remains set until the ADC conversion is stopped. To stop ADC
conversion at any time, write ‘0’ to this bit. The ADC stops acquiring data after the
current conversion is finished or if the ADC is waiting during extended acquisition time,
the ADC stops immediately.
5 ADCFG ADC Conversion Configuration Register Select.
ADCFG = 0: The ADDATA register points to the data buffers. The ADIDX[4:0] bits
determine which data buffer is currently being accessed. When ADCFG=0 and
ADCAVG = 0, ADDATA is read only.
ADCFG = 1: The ADDATA register points to the ADC sequence configuration registers.
The ADIDX[4:0] bits determine which configuration register is currently being accessed.
When ADCFG=1, ADDATA has read/write access.
4:0 ADIDX[4:0] ADC Register Index Bits [4:0]. These bits together with ADCFG and ADCAVG select
the source / destination for ADDATA access. This register value is auto-incremented on
successive access (read/write) of ADDATA register. When ADCFG=1, ADIDX [4:0] are
used to address one of 24 configuration registers. When ADCFG=0, ADIDX [4:0] are
used to select one of 25 data buffers.
ADCFG=1, ADCAVG=0: ADIDX[4:0] used to address one of 24 configuration registers
ADCFG=0, ADCAVG=1: ADIDX[4:0] used to address one of 24 average configurations
ADCFG=0, ADCAVG=0: ADIDX[4:0] used to select one of 25 data buffers.
7.2.3 – PIN Select Register (PINSEL)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PINSEL[15:0]
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Each bit in this register corresponds to an ADC input pin. When these bits are set the corresponding pins are
dedicated for ADC use. On POR, the pin selection register is 0000h which corresponds to GP0 to GP15 being GPIO.
For using these pins as ADC input, Sample and Hold or Quick Trip inputs the corresponding PINSEL bit should be
set to ‘1’.