8 – receiving data, 9 – clock stretching, Ds4830a user’s guide – Maxim Integrated DS4830A Optical Microcontroller User Manual

Page 100

DS4830A User’s Guide

100

11.1.8 – Receiving Data
The I

C Slave Controller enters data reception mode after receiving a matching slave address with the R/

W bit set to

0. The steps of data reception are shown in Figure 11-2 and Figure 11-4. The reception process begins when the I

slave controller detects the first rising edge of SCL. This rising edge sets I2CBUSY bit to ‘1’ and clocks the first bit
(MSB) of data from SDA into the data shift register.

11.1.8.1 – Receiving Data in Normal Mode
When receiving data, the I

C slave controller uses a double buffer consisting of the I2CBUF_S register and the shift

C module to continue receiving data while the previous data byte is being processed.

After a byte (8 bits) of data is received, the I

C slave controller attempts to copy the received data from the shift

1. If I2CBUF_S is empty, the I

C slave controller copies the data from the shift register into I2CBUF_S. The

I2CRXI flag is set to indicate a received byte is ready for reading. The setting of I2CRXI can generate an
interrupt if enabled. Software can now read data from the I2CBUS_S.

2. If I2CBUF_S is full, the data in the shift register cannot be copied into I2CBUF_S. This causes a receive

overrun condition. The receive overrun flag, I2CROI is set which can generate an interrupt if enabled.
I2CBUF_S can be full if it is not read by software following the reception of a previous byte.

When the receive overrun occurs (I2CROI = 1), any new incoming data is not shifted into the I

C slave controller.

The controller responds to any bytes received with a NACK regardless of the setting of the I2CACK bit. The receive
overrun condition and the I2CROI flag can only be cleared by software reading received first byte from I2CBUF_S.
When the receive overrun condition is cleared, the I2C slave controller copies the second byte that is received into
I2CBUF, and again sets I2CRXI to indicate a byte of data is received. The I

C slave controller resumes its normal

operation in the next SCL clock cycle after I2CROI is cleared. To avoid losing any data, I2CROI must to be cleared
prior to the first SCL clock rising edge of the next byte.

After the 9

bit of any byte has been received, the I2CBUSY bit is cleared to indicate that the controller is no longer

participating in a data transaction. The value in I2CACK is transmitted to the host on the 9

SCL clock cycle,

assuming the I

C slave controller is not operating in receive overrun.

11.1.8.2 – Receiving Data in Advanced Mode
As shown in Figure 11-4, when receive FIFO is enabled, the incoming data is copied into the FIFO. The receive
FIFO will set flags in the I2CRXFST register when the FIFO is empty, half full with 4 bytes, or full with 8 bytes of
received data. Interrupts can be generated for these events if the appropriate bits are set in the I2CRXFIE register.
The receive FIFO is read one word at a time by reading the I2CBUF_S register.

11.1.9 – Clock Stretching
If slave device cannot receive or transmit another complete byte of data, it may hold SCL low, forcing the master to
wait. Data transfer continues when the slave is ready for next byte of data after releasing SCL.

The I

C slave controller is capable of holding SCL low at the completion of each byte being transferred. If the I

Clock Stretch Enable bit (I2CSTREN) is set to a 1, the I

C controller holds SCL low after the 8

or 9

clock pulse as

configured in the I

C Clock Stretch Select bit (I2CSTRS). If I2CSTRS=0, the I

C controller holds SCL low after the

falling edge of the 9

clock pulse. If I2CSTRS=1, the I

C controller holds SCL low after the falling edge of the 8th

clock pulse. When the I

C controller is holding SCL low, the I

C Clock Stretch Interrupt bit (I2CSTRI) is set. The I

slave controller holds SCL low until I2CSTRI is cleared to '0' by software. Figure 11-5 shows the I

C slave controller

clock stretching after receiving the 9

clock of a byte.