Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 179)

DS4830A User’s Guide
179
SECTION 22 – IN-SYSTEM PROGRAMMING
The DS4830A contains an internal bootstrap loader utilizing the JTAG or I
2
C interfaces. As a result, system software
can be upgraded in-system, eliminating the need for a costly hardware retrofit when software updates are required.
After each device reset, DS4830A ROM code is executed which determines if bootloader operation is desired.
Figure 22-1 provides information on how the DS4830A enters into bootloader operation.
Any Device Reset Occurs
Reset Device.
Begin Boot ROM code
execution at
8000h.
ROM Code enable the
Slave I 2 C Interface
Is JTAG_SPE
bit set?
Is I2C_SPE
bit set?
Jump to user
code
(flash) at 0000h,
Set PSS{1:0] = 01
Bootloader
Exit Bootloader
Delay 320 Clock Cycles
Set PWL and ROD bits.
Yes
No
Yes
No
Is PSS[1:0]
!= 1X
Exit Loader
Command
Yes
No
Figure 22-1: Entering Bootloader Operation
22.1 – Detailed Description
Following every reset, device ROM code is executed which determines if the DS4830A should enter into a
bootloader mode. First, the ICDF register, which is not cleared by a reset, is read to see if the System Programming
Enable (SPE) bit is set. See the Entering JTAG Bootloader section for more details on setting the SPE bit. If SPE is
set, the DS4830A will enter into bootloader operation.
If SPE is not set, the DS4830A then enables the slave I
2
C interface. The I2C_SPE bit in the I2C_SPB register is
read to determine if I
2
C bootloader operation is desired. The I2C_SPB register is not cleared by a reset. See the
Entering I
2
C Bootloader section for more details on setting the I2C_SPE bit. If I2C_SPE is set, the DS4830A will set
the PSS[1:0] bits to 01, which designates I
2
C bootloader, and enter bootloader operation.
If none of the preceding conditions have been met, the DS4830A ROM code will be complete. The DS4830A will
then jump to program memory location 0000h and begin normal program execution.