Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 3)

DS4830A User’s Guide
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3.18 – General Register (GR, 0Eh[05h]) ........................................................................................................................... 31
3.19 – General Register Low Byte (GRL, 0Eh[06h]) ......................................................................................................... 31
3.20 – Frame Pointer Base Register (BP, 0Eh[07h]) ........................................................................................................ 31
3.21 – General Register Byte-Swapped (GRS, 0Eh[08h]) ................................................................................................ 32
3.22 – General Register High Byte (GRH, 0Eh[09h]) ........................................................................................................ 32
3.23 – General Register Sign Extended Low Byte (GRXL, 0Eh[0Ah]) .............................................................................. 32
3.24 – Frame Pointer Register (FP, 0Eh[0Bh]) ................................................................................................................. 32
3.25 – Data Pointer 0 Register (DP[0], 0Fh[03h]) ............................................................................................................. 32
3.26 – Data Pointer 1 Register (DP[1], 0Fh[07h]) ............................................................................................................. 32
SECTION 4 – PERIPHERAL REGISTER DESCRIPTIONS ................................................................................................. 33
4.1 – Module 0 Peripheral Registers ................................................................................................................................. 34
4.2 – Module 1 Peripheral Registers ................................................................................................................................. 35
4.3 – Module 2 Peripheral Registers ................................................................................................................................. 36
4.4 – Module 3 Peripheral Registers ................................................................................................................................. 37
4.5 – Module 4 Peripheral Registers ................................................................................................................................. 38
4.6 – Module 5 Peripheral Registers ................................................................................................................................. 39
SECTION 5 – INTERRUPTS ................................................................................................................................................ 40
5.1 – Servicing Interrupts ................................................................................................................................................... 41
5.2 – Module Interrupt Identification Registers .................................................................................................................. 42
5.3 – Interrupt System Operation ...................................................................................................................................... 43
5.3.1 – Synchronous vs. Asynchronous Interrupt Sources ............................................................................................ 44
5.3.2 – Interrupt Prioritization by Software ..................................................................................................................... 44
5.3.3 – Interrupt Exception Window ............................................................................................................................... 44
SECTION 6 – DIGITAL-TO-ANALOG CONVERTER (DAC) ................................................................................................ 45
6.1 – Detailed Description ................................................................................................................................................. 45
6.1.1 – Reference Selection .......................................................................................................................................... 46
6.2 – DAC Register Descriptions ....................................................................................................................................... 46
6.2.1 – DAC Configuration Register (DACCFG) ............................................................................................................ 46
6.2.2 – DAC Data Registers (DACD0-DACD7) ............................................................................................................. 47
6.2.3 – Reference Pin Configuration Register (RPCFG) .............................................................................................. 47
6.3 – DAC Code Examples ................................................................................................................................................ 47
SECTION 7 – ANALOG-TO-DIGITAL CONVERTER (ADC) ................................................................................................ 48
7.1 – Detailed Description ................................................................................................................................................. 48
7.1.1 – ADC Controller ................................................................................................................................................... 48
7.1.2 – ADC Conversion Sequencing ............................................................................................................................ 49
7.1.3 – Internal Die Temperature Conversion ................................................................................................................ 50
7.1.4 – Sample and Hold Conversion ............................................................................................................................ 51
7.1.5 – ADC Frame Sequence ....................................................................................................................................... 51
7.1.6 – ADC Reference .................................................................................................................................................. 51
7.1.7 – ADC Conversion Time ....................................................................................................................................... 52
7.1.8 – Location Override ............................................................................................................................................... 53
7.1. 9 – Averaging .......................................................................................................................................................... 53