Maxim Integrated DS4830A Optical Microcontroller - Manual (Page 142)

DS4830A User’s Guide
142
15.2.5 – GPIO Port External Interrupt Flag Register (EIF0, EIF1, EIF2, and EIF6)
Bit # 7 6 5 4 3 2 1 0
Name IFPp_7 IFPp_6 IFPp_5 IFPp_4 IFPp_3 IFPp_2 IFPp_1 IFPp_0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
These bits are set when a negative edge (IESPp.n = 1) or a positive edge (IESPp.n = 0) is detected on the Pp.n pin.
Setting any of the bits to 1 will generate an interrupt to the CPU if the corresponding interrupt is enabled. These bits
will remain set until cleared by software or a reset. These bits must be cleared by software before exiting the
interrupt service routine or another interrupt will be generated as long as the bit remains set.
15.2.6 – GPIO Port External Interrupt Enable Register (EIE0, EIE1, EIE2, and EIE6)
Bit # 7 6 5 4 3 2 1 0
Name IEPp_7 IEPp_6 IEPp_5 IEPp_4 IEPp_3 IEPp_2 IEPp_1 IEPp_0
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Setting any of these bits to 1 will enable the corresponding external interrupt. Clearing any of the bits to 0 will disable
the corresponding interrupt function.
15.3 – GPIO Code Example
15.3.1 – GPIO Pin as Output
//set pin 6.4 as a high output
PD6 |= 0x10;
//set direction PD6.4 to 1 for an output
PO6 |= 0x10; //set the output PO6.4 high
15.3.2 – GPIO High-Impedance Input
//set pin 6.4 as a high-impedance input
PD6 &= ~0x10;
//set direction PD6.4 to 0 for input
PO6 &= ~0x10; //set PO6.4 low to disable weak pullup
15.3.3 – GPIO Weak Pullup Input
//enable the pin 6.4 weak pullup
PD6 &= ~0x10;
//set direction PD6.4 to 0 for input
PO6 |= 0x10; //set PO6.4 high to enable weak pullup
15.3.4 – GPIO Open-Drain Output
//configure pin6.4 as port ‘Open Drain’
PO6 &= ~0x10;
// set the PO6.4 to the logic ‘0’
PD6 |= 0x10; // this will configure P6.4 as output and drive logic ‘0’
PD6 &= ~0x10; // this will configure P6.4 as input with high impedance.
In summary, the GPIO output can be set to the ‘Open Drain’ by doing the following method
1. Set the POp.n to the logic ‘0’.
2. Toggle the direction register PDp.n between the input and output.
This causes the pin to alternate between logic ‘0’ (PDp.n = 1) and ‘high impedance’ (PDp.n = 0).